One possible allocation is shown in Listing 2.5; it considers why an embedded engineer might want greater section allocation control.
Listing 2.5: Possible section allocation.
MEMORY {
ROM: origin = 0x00000h, length = 0x000100h
FLASH: origin = 0x00110h, length = 0x004000h
RAMB0: origin = 0x05000h, length = 0x020000h
RAMB1: origin = 0x25000h, length = 0x200000h
}
SECTION {
.rodata: ROM
_loader: FLASH
_wflash: FLASH
_monitor: RAMB0
.sbss (ALIGN 4): RAMB0
.sdata (ALIGN 4): RAMB0
.text: RAMB1
.bss (ALIGN 4): RAMB1
.data (ALIGN 4): RAMB1
}
This program allocation is shown in Figure 2.8. The section allocation strategies applied include the following:
· The .rodata section contains system initialization parameters. Most likely these default values never change; therefore, allocate this section to ROM.
· The loader program is usually part of the system program that executes at startup. The _loader and the _wflash sections are allocated into flash memory because the loader code can be updated with new versions that understand more object formats. You need the flash memory programmer for this purpose, which can also be updated. Therefore, section _wflash is allocated into the flash memory as well.
· The embedded programmer interacts with the monitor program to probe system execution states and help debug application code; therefore, it should be responsive to user commands. SDRAM is faster than DRAM, with shorter access time. Therefore, section _monitor is allocated into RAMB0.
· RAMB0 still has space left to accommodate both sections.sbss and.sdata. The allocation strategy for these two sections is to use the leftover fast memory fully.
· The remaining sections (.text, .bss, and .data) are allocated into RAMB1, which is the only memory that can accommodate all of these large sections.
Figure 2.8: Mapping an executable image into the target system.
2.5 Points to Remember
· The linker performs symbol resolution and symbol relocation.
· An embedded programmer must understand the exact memory layout of the target system towards which development is aimed.
· An executable target image is comprised of multiple program sections.
· The programmer can describe the physical memory, such as its size and its mapping address, to the linker using the linker command file. The programmer can also instruct the linker on combining input sections into output sections and placing the output program sections using the linker command file.
· Each program section can reside in different types of physical memory, based on how the section is used. Program code (or.text section) can stay in ROM, flash, and RAM during execution. Program data (or.data section) must stay in RAM during execution.
Chapter 3: Embedded System Initialization
3.1 Introduction
Booting the target system, whether a third-party evaluation board or a custom design, can be a mystery to many newcomers. Indeed, it is daunting to pick up a programmers reference manual for the target board and pore over tables of memory addresses and registers or to review the hardware component interconnection diagrams, wondering what it all means, what to do with the information (some of which makes little sense), and how to relate the information to running an image on the target system.
Questions to resolve at this stage are
· how to load the image onto the target system,
· where in memory to load the image,
· how to initiate program execution, and
· how the program produces recognizable output.
We answer these questions in this chapter and hopefully reduce frustration by demystifying the booting and initialization process of embedded systems.
Chapter 2 discusses constructing an executable image with multiple program sections according to the target system memory layout. After the final image is successfully built and
residing on the host system, the next step is to execute it on the target.
The focus of this chapter is
· image transfer from the host to the target system,
· the embedded monitor and debug agent,
· the target system loader,
· the embedded system booting process,
· various initialization procedures, and
· an introduction to BDM and JTAG interfaces.
3.2 Target System Tools and Image Transfer
loading the image· Programming the entire image into the EEPROM or flash memory.
· Downloading the image over either a serial (typically RS-232) or network connection. This process requires the presence of a data transfer utility program on the host system, as well as the presence of a target loader, an embedded monitor, or a target debug agent on the target system.
· Downloading the image through either a JTAG or BDM interface (discussed in section 3.5).
These approaches are the most common, and this list is by no means comprehensive. Some of the possible host-to-target connectivity solutions are shown in Figure 2.1. Figure 3.1 exemplifies a target embedded system. We refer to the ELF image format (introduced in Chapter 2) exclusively throughout this chapter.